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Course Outline
RISC-V Architecture Fundamentals and Ecosystem Overview
RISC-V ISA Landscape and Industry Adoption
- Understanding the open ISA philosophy and the RISC-V International standardization framework
- Building a mental model of RISC-V: Load-Store architecture, register files, and byte ordering conventions
- Analyzing trade-offs between RISC-V, ARM, x86, and POWER architectures for heterogeneous computing environments
- Evaluating ecosystem maturity through key players like SiFive, T-Head, Western Digital, and the expanding open-source silicon community
- Examining standardized interfaces: The RISC-V Privileged ISA and Machine Software Abstraction Layer (MSBL)
Memory Models and ABI Compliance
- Exploring the Unprivileged Architecture specification, including CSR maps, exception handling mechanisms, and memory hierarchies
- Mastering RV32I/RV64I instruction sets and ensuring ABI compliance for cross-platform binary portability
- Implementing memory ordering conventions and barrier instructions essential for multiprocessor systems
RISC-V Assembly Programming and Compiler Toolchain
Low-Level Instruction Programming
- Working with base integer (I), Multiply/Divide (M), and Atomic operations (A) extensions
- Developing bitness-aware programming strategies for both 32-bit and 64-bit RISC-V targets
- Managing calling conventions and stack frames tailored for embedded and real-time software systems
Compiler Toolchain Proficiency
- Navigating LLVM-based compiler tools: utilizing Clang, LLVM, and Binutils for RISC-V cross-compilation
- Configuring linker scripts, sections, and memory layouts for bare-metal and RTOS environments
- Leveraging compiler intrinsics, optimizing code via various optimization levels, and performing profiling-driven tuning
- Gaining expertise in open-source toolchain workflows: building, testing, and packaging custom GCC/Clang toolchains
Embedded Systems Development and Real-Time Operating Systems
Bare-Metal and RTOS Programming
- Utilizing Rust systems programming for RISC-V: mastering zero-cost abstractions, unsafe memory management, and bare-metal development
- Navigating No-Std environments: creating custom linkers, developing device drivers, and handling memory-mapped I/O
- Developing BSPs using Zephyr RTOS and Buildroot for RISC-V targets
- Interfacing with peripherals: programming GPIO, I2C, SPI, UART, and DMA controllers
Power and Performance Optimization
- Implementing clock gating, managing power domains, and optimizing low-power modes
- Conducting cycle-accurate performance analysis using simulation profilers and hardware performance counters
- Tuning real-time interrupt latency to meet the requirements of safety-critical applications
Linux Kernel and Bootloader Development for RISC-V
Boot Firmware and Bootloader Ecosystem
- Developing bootloader firmware based on the OpenSBI (SBI specification implementation)
- Implementing UEFI/EDK II on RISC-V to build modern firmware boot stacks
- Porting Coreboot and U-Boot for RISC-V single-board computers
Linux Kernel Integration
- Contributing to the RISC-V mainline kernel: handling device tree overlays, CPU topology, and developing AIA interrupt controller drivers
- Creating vendor BSPs and configuring kernels for custom SoC platforms
- Enabling file system support, networking stacks, and containerization (Docker, Kubernetes) on RISC-V host systems
RISC-V SoC Design and FPGA Prototyping
Multicore SoC Architecture and Integration
- Applying Network-on-Chip (NoC) design methodologies for RISC-V multi-core processors
- Implementing Axi4/CHI cache coherence and inter-processor communication protocols
- Integrating open-source IPs from OpenCores, the ChIPS Framework, and vendor RTL components
- Designing bus matrices and integrating memory controllers (DDR, SRAM, eMMC, PCIe)
FPGA-Based Processor Prototyping
- Synthesizing and implementing RISC-V cores (e.g., BOOM, VexRiscv, PULP) on FPGAs
- Employing SystemVerilog Assertions (SVA) and UVM-based functional verification methodologies
- Utilizing formal verification tools and property-based testing for rigorous RISC-V core validation
RISC-V Vector Extensions and Domain-Specific Acceleration
RVV (RISC-V Vector) Extension Deep Dive
- Exploring vector load/store operations, vector-fused multiply-add (VFMA), and matrix computation acceleration
- Leveraging variable-length vector operations (VL, VLEN) for workload-optimized SIMD execution
- Utilizing vector mask operations, segment control, and flexible data types to support DSP and ML workloads
Custom DSP and Domain-Specific Instruction Design
- Designing domain-specific accelerators using custom extensions and CBAR-based operand interfaces
- Modifying compiler frontends to enable custom instruction generation and code emission
- Developing hardware-software partitioning strategies for integrating accelerators into production SoCs
AI Acceleration and Edge Machine Learning on RISC-V
NPU Design and Integration for RISC-V Processors
- Architecting Neural Processing Units (NPUs) using systolic arrays, tensor cores, and weight compression for on-chip AI acceleration
- Applying model quantization techniques (INT8, INT4, FP8) for efficient edge deployment on RISC-V
- Ensuring framework compatibility with TensorFlow Lite Micro, ONNX Runtime, and PyTorch Edge on RISC-V targets
Heterogeneous Computing for AI Workloads
- Co-designing RISC-V host CPUs paired with AI accelerator NPUs for real-time inference pipelines
- Optimizing memory subsystems, including HBM/DDR bandwidth management for ML model weights and activations
- Managing thermal constraints and power budgets for edge AI inference systems
Hardware Security and Confidential Computing on RISC-V
Physical Memory Protection and Trusted Execution
- Implementing Physical Memory Protection (PMP) and securing page table walkers
- Deploying Secure Enclave/TEE architectures for RISC-V, including OP-TEE integration and SEV-class trusted execution environments
- Securing the boot chain: establishing a root of trust, implementing secure boot, and verifying measured launch attestation
Cryptographic Acceleration
- Leveraging RISC-V cryptographic extensions (Zk, Zkr, K) for accelerating SHA, AES, RSA, RSA-PSS, and ECC operations
- Integrating Post-Quantum Cryptography (PQC) to future-proof next-generation RISC-V processors
- Mitigating side-channel attacks through constant-time programming, masking techniques, and hardware random number generators
Advanced Custom Architecture and ISA Extension Design
Domain-Specific Architecture and Custom Instruction Extensions
- Mastering ISA extension design: encoding, creating encoding tables, analyzing ABI impacts, and submitting to the RISC-V International specification process
- Designing custom register files with CBAR (Custom Base Address Registers) for efficient operand dispatch
- Optimizing instruction pipelining, hazard detection, and pipeline modifications for custom extensions
Verification and Signoff of Custom Architecture Modifications
- Designing testbenches for custom extensions using directed versus constraint-random stimulus generation
- Establishing regression testing frameworks and coverage-driven verification for architectural modifications
- Conducting interoperability testing to ensure custom instructions function correctly within established ABI constraints
Safety-Critical and Automotive RISC-V Applications
Functional Safety and Automotive Standards Compliance
- Achieving ISO 26262 functional safety compliance for automotive processors based on RISC-V
- Defining ASIL-Q classifications and developing safety manuals for RISC-V silicon IP
- Ensuring deterministic interrupt handling, lockstep core pairing, and robust memory protection for safety-critical RISC-V systems
Industrial Real-Time and Edge Computing Applications
- Meeting IEC 61508 SIL compliance and implementing deterministic scheduling on RISC-V multicore platforms
- Developing Industrial IoT gateways with RISC-V, focusing on connectivity, edge analytics, and OTA firmware update systems
Capstone Project: End-to-End RISC-V System Development
Full Lifecycle Project
- Architecture specification: Designing ISA extensions and core configurations for a defined use case
- RTL implementation in SystemVerilog, complete with UVM testbenches and formal verification coverage
- FPGA prototyping, boot firmware development, and integration of the bare-metal driver stack
- Customizing Linux BSPs and toolchains for the bespoke RISC-V core
- Deploying AI workloads: integrating NPUs, applying model quantization, and conducting performance benchmarking
- Validating security: enforcing PMP, implementing secure boot, and benchmarking cryptographic acceleration
- Delivering technical architecture documentation, performing IP strategy analysis, and presenting to cross-functional teams
Requirements
None.
21 Hours
Testimonials (2)
The explanations and interactivity of the trainer, he really brought the subject well; and even-though I was probably not experienced enough, I did learn a lot from it!
Pieter Bruynseels - Spot Buy Center BV
Course - Design Patterns
I liked the platform we used. It was really nice and easy to use. I liked the typescript section, the part about namespaces and modules.
